1. Field of the Invention
The present invention relates to a method of altering the contents of memory cells of an electrically alterable non-volatile semiconductor memory device (hereinafter referred to as EEPROM), which is applicable to an EEPROM and a semiconductor device incorporating the EEPROM.
2. Description of the Related Art
The following documents are relating to the present invention.
Document No. 1: JP-A-61-127179 entitled "Electrically Programmable Memory Device for a Single Transistor and Method of Fabricating the Same" PA1 Document No. 2: "Design of CMOS ultra-LSI" edited by Takuo Sugano, 1989, pp. 172-173 PA1 Document No. 3: "The Present State and Future Prospects of Flash Memory", The Institute of Electronics, Information and Communication Engineers of Japan, ICD91-134 PA1 Document No. 4: "Flash Memory With Negative Scheme", The Institute of Electronics, Information and Communication Engineers of Japan, ICD91-135 PA1 Document No. 5: "The Cell Technology of a 16M Flash Memory is converging, Nikkei Micro-Device, July 1991 PA1 Document No. 6: "Flash EEPROM Cell Scaling Based on Tunnel Oxide Thinning Limitations" 1991 VLSI Symposium Technology PA1 Document No. 7: "Si Thermally-oxidized Film and its Interface" pp. 355-371 Realize Corp. PA1 Document No. 8: JP-A-3-219496 entitled "Non-volatile Semiconductor Memory Device" PA1 Document No. 9: U.S. Pat. No. 5,122,985
Many proposals for an electrically alterable non-volatile memory cell (hereinafter referred to as EEPROM memory cell) have been made from the early 1980s. The typical one of them is a memory cell having a floating gate as a charge holding layer as disclosed in Documents Nos. 1, 2, 3 and 4.
The EEPROM memory cell having a floating gate includes a crystalline semiconductor Si substrate, source and drain regions formed on the substrate by doping impurities having an opposite conductivity type to that of the impurities in the substrate (where the substrate is a p-type substrate doped with boron(B), the source and drain regions are n-type layers doped with arsenic (As) or phosphorus (P)), a channel region between the source and drain through which minority carriers pass, a thin oxide film in contact with the upper surface of the channel region, a floating gate made of conductive polysilicon in contact with the upper surface of the thin oxide film, and a control gate made of polysilicon in contact with the upper surface of the floating gate.
The theory of memorizing the above EEPROM is that the threshold voltage of the memory cell viewed from the control gate is altered by injecting and storing charges (electrons or holes) in the floating gate (the threshold voltage is defined as the minimum voltage applied to the control gate required for a memory cell to make a detectable response). An example of the prior art method of injecting charges into the floating gate is shown in FIGS. 8 and 9 (This prior art is disclosed in Document No. 1 as a prior art and in Document No. 2).
The prior art memory cell array shown in FIGS. 8 and 9 requires a single MOS enhancement N-channel transistor (20, 21, 22 or 23 in FIG. 8) and a single memory cell (24, 25, 26 or 27 in FIG. 8) having a floating gate for selecting and storing 1-bit information. The prior art shown in FIG. 8 can select and store the information corresponding to 4 (four) bits. In FIG. 8, a word line 200 is connected to the gate of each of transistors 18, 20 and 21. A word line 201 is connected to the gate of each of transistors 19, 22 and 23. A bit line 203 is connected to the drain of each of the transistors 20 and 22. A bit line 204 is connected to the drain of each of the transistors 21 and 23. The drain of each of the transistors 18 and 19, which is a MOS enhancement channel transistor for selecting one byte, is connected to a sense line 202. The threshold voltage of each of the transistors 18, 19, 20, 21, 22 and 23 is e.g. 1 V (volts). The source of the transistor 18 is connected to the control gate 206 of each of the transistors 24 and 25, and the source of the transistor 19 is connected to the control gate 207 of each of the transistors 26 and 27. The source of each of the transistors 20, 21, 22 and 23 is connected to the drain of an associated one of the transistors 24, 25, 26 and 27 through an n-type impurity diffused layer.
FIG. 9 is a sectional view taken along line IX--IX in FIG. 8 and corresponds to 1 bit. In FIG. 9, reference numeral 220 denotes a P-type Si substrate; 205', 208 and 203' an N-type impurity diffused layer; 223 and 224 a Si thermally-oxidized film (gate oxide film) on the channel; and 225 a Si thermally-oxidized film which is sufficiently thinner than any of the oxide films 223 and 224 (e.g. the films 223 and 224 are 50 nm thick whereas the film 225 is 10 nm thick). Reference numeral 206 denotes a control gate made of e.g. polysilicon; 227 an interlayer insulating film (e.g. thermally oxidized film having a thickness of about 25 nm); and 200 a gate made of e.g. polysilicon. Reference 228 denotes an insulating layer; 203 a bit line mainly made of aluminum (Al); and 229 a contact connecting the bit line 203 with the N-type impurity diffused layer 203'. While the polysilicons of the gates 200 and 206 are electrically connected to other memory cells, the floating gate is electrically insulated from the other memory cells.
The electric equivalent circuit of the memory cell shown in FIGS. 8 and 9 is shown in FIG. 10. In FIG. 10, a voltage Vg is applied to a control gate 206; Vd to a drain 208, Vs to a source 205; and Vsub to a substrate 220. In FIG. 9, the oxide films 224 and 225 and the interlayer insulating film 227 can be represented by capacitance in the electrical viewpoint. A capacitance between the floating gate 226 and the control gate 206 is denoted by Cip; a capacitance between the floating gate 226 and the drain 208 by Cd; a capacitance between the floating gate 226 and the source 205 by Cs; and a capacitance between the floating gate 226 and the substrate by Csub. From the conservation law of electric charge, the voltage Vf at the floating gate 226 can be expressed by EQU Cip (Vg-Vf)=Cs (Vf-Vs)+Csub (Vf-Vsub)+Cd (Vf-Vd) (1)
In Equation (1), if Vs=Vsub=Vd=0 V, EQU Vf=Vg.times.Rp (2)
where Rp=Cip/(Cip+Cd+Csub+Cs). Rp is called a coupling ratio, generally Rp=0.55 to 0.7.
An explanation will be given of the method of altering and reading the prior art memory cell shown in FIGS. 8 and 9. Table 1 shows examples of the node voltages in each operation mode. Altering includes writing and erasing. Now, the case where the memory cell 24 is selected is taken as an example.
TABLE 1 __________________________________________________________________________ each node voltage operation mode 200 201 202 203 204 205 206 208 225 __________________________________________________________________________ alter write +20v 0v 0v +20v 0v open 0v +18v 0v erase +20v 0v +20v 0v 0v 0v +18v 0v 0v read +5v 0v +3v +2v 0v 0v +3v +2v 0v __________________________________________________________________________
In a write operation for the memory cell 24, for example, 20 V is applied to the word line 200, 0 V is applied to the sense line 202, 20 V is applied to the bit line 203 and the source 205 is opened. Thus, the transistors 18, 20 and 21 turn on so that the control gate 206 is at 0 V and the drain 208 is at about 18 V (20 V is the threshold voltage (including substrate effect) of the transistor 20). As a result, a voltage of about 7 V is induced in the floating gate 226. Since the oxide film is as thin as 10 nm, a Flower-Nordheim tunnel (FN tunnel) current due to a potential difference between the floating gate 226 and the source 208 flows through the thin oxide film 225. Generally, the FN tunnel current flows when an electric field of 10 MeV/cm or larger is applied to the thin oxide film. This FN tunnel current causes holes to be injected from the drain 208 into the floating gate 226. This lowers the threshold voltage of the memory cell (For example, when the initial threshold voltage of the memory cell is 2 V, the threshold voltage after writing is -2 V to -3 V). Then, the bit line 204 is at 0 V and the word line 201 is at 0 V so that a high voltage is not applied to the memory cells other than the memory cell 24, and write for these memory cells is not carried out.
In an erasing operation for the memory cell 24, for example, 0 V is applied to the word line 200, 20 V is applied to the sense line 202, and 0 V is applied to the bit line 203 so that the control gate 206 is at about 18 V and the drain is at 0 V. Thus, about 11 V is induced in the floating gate 226. Then, the FN tunnel current flowing through the oxide film 225 causes electrons to be injected into the floating gate 226. This enhances the threshold voltage of the memory cell (e.g. to 6 to 7 V). Then, the word line 201 is at 0 V so that the gate 207 is opened, and so the memory cells 26 and 27 are not erased. On the other hand, like the memory cell 24, the memory cell 25 will be erased because the bit line 204 is at 0 V. In short, in the erasing operation, all the memory cells connected to the same node or the gate 206 are erased to enhance their threshold voltage.
In a read operation for the memory cell 24, for example, 5 V is applied to the word line 200, 3 V is applied to the sense line 202, and 2 V is applied to the bit line 203. Thus, the transistors 18 and 20 turn on so that the drain 208 of the memory cell 24 is at 2 V and the control gate 206 thereof is at 5 V. Then, if the threshold voltage of the memory cell is as high as 6-7 V, the memory cell 24 is "off" so that no current flows between its source and drain. If the threshold voltage of the memory cell 24 is as low as -2 to 3 V, the memory cell 24 is "on" so that a current flows between its source and drain. Read of the stored information can be made on the basis of the presence or absence (large or small) of the current.
The problem of the above prior art is as follows. In the prior art, in altering the memory cell, the FN tunnel current is used to inject charges. So the altering operation only requires a relatively small current e.g. 10 to 1000 pA (pico-ampere) for one memory cell. This is an advantage of the prior art. But, the prior art has the following defect. In order to make selective writing for the memory array, separation transistors such as the transistors 20, 21, 22 and 23 in FIG. 8 are required to separate the memory cells 24, 25, 26 and 27 from one another (It can be understood that if the transistors 20, 21, 22 and 23 are not provided in FIG. 1, writing of the memory cell 24 results in writing of the memory cell 26). Provision of one separation transistor for one bit requires an occupying area of e.g. 80-150 .mu.m.sup.2. This defect hinders large-scale integration of memory cells.
The second prior art memory cell array is shown in FIGS. 11 and 12. In order to overcome the defect of the prior art described above, this prior art uses channel hot electrons in writing so that no additional transistor is required. This prior art is disclosed in e.g. Documents Nos. 1, 3, 4 and 5. In FIG. 11, a word line 300 is connected to the gate of each of memory cells 30 and 31, and a word line 301 is connected to the gate of each of memory cells 32 and 33. A bit line 302 is connected to the drain of each of the memory cells 30 and 32, and a bit line 303 is connected to the drain of each of the memory cells 31 and 33. A source line 304 is connected to the source of each of the memory cells 30, 31, 32 and 33.
FIG. 12 is a sectional view taken along line XII--XII in FIG. 11 and corresponds to 1 bit. In FIG. 12, reference numeral 305 denotes a P-type Si substrate; 304' and 302' an N-type impurity diffusion layer; and 306 a Si thermally-oxidized film (having a thickness of e.g. 10 nm) on the channel. Reference numeral 309 denotes a floating gate made of e.g. polysilicon; and 300 a control gate made of e.g. polysilicon. Reference numeral 307 denotes an insulating film (made of nitride or oxide having a thickness of e.g. 25 nm) interposed between the control gate and the floating gate 309. Reference numeral 310 denotes an insulating layer; 302 a bit line mainly made of aluminum (Al); and 308 a contact connecting the bit line 302 with the N-type impurity diffusion layer 302'.
An explanation will be given of the method of rewriting and reading the prior art memory cell shown in FIGS. 11 and 12. Table 2 shows examples of the node voltages in each operation mode which are disclosed in Document No. 4.
TABLE 2 ______________________________________ each node electrode operation mode 300 301 302 303 304 ______________________________________ alter write 12v 0v 5v 0v 0v erase -9v 0v open open 5v read 5v 0v 1v 0v 0v ______________________________________
Now it is assumed that the threshold voltage is e.g. 2 V when the floating gate holds no charge. In a writing operation for the memory cell 30 selected in FIG. 11, 12 V is applied to the word line 300; 0 V to the word line 301; 5 V to the bit line 302; 0 V to the bit line 303; and 0 V to the source line 304. Then, with the coupling ratio Rp of 0.6, about 7 V is induced in the floating gate 309. Thus, an electron channel is formed between the drain and source of the memory cell 30. In addition, because the gate voltage and drain voltage are high, hot electrons are created in the vicinity of the drain. The hot electrons pass over the potential barrier between the silicon and gate oxide film to be injected into the floating gate 309.
Such a phenomenon is described in detail in Document No. 7. The injection of channel hot electrons (referred to as CHEs) boosts the threshold voltage of the memory cell 30 to e.g. 6 to 8 V. Then, a current of 300 .mu.A to 1 mA flows between the drain and source of the memory cell 30. Since the word line 301 is at 0 V and the bit line 303 is at 0 V, write for the memory cells 31, 32 and 33 is not carried out.
In an erasing operation for the memory cell 30, e.g. -9 V is applied to the word line 300, e.g. 0 V is applied to the word line 301, the bit lines 302 and 303 are opened, and 5 V is applied to the source line 304. Then, about -7 V is induced in the floating gate 309 so that electrons are drawn out from the floating gate 309 to the source 304 (=304') owing to the FN tunnel current via the gate oxide film 306. By controlling the amount of the electrons as drawn by a suitable control circuit, the threshold voltage of the memory cell 30 is adjusted to be lowered to a positive low value of 2 to 3 V. This adjustment is necessary because if the threshold voltage is lowered to 0 V or less, in a read operation, a current will flow between the source and drain of a non-selected memory cell, resulting in erroneous read. For this reason, the threshold voltage is adjusted to the above positive value. Additionally, it should be noted that the memory cell 31 will be also erased when the memory cell 30 is erased. Namely, the memory cells on the same word line as the selected memory cell lies will be erased simultaneously. On the contrary, the memory cells 32 and 33 will not be erased because the word line 301 is at 0 V.
In a read operation for the memory cell 30, e.g. 5 V is applied to the word line 300, 0 V to the word line 301, e.g. 1 V to the bit line 302, 0 V to the bit line 303, and 0 V to the source line 304. Then, if the threshold voltage of the memory cell 30 is high (e.g. 6 to 8 V), the memory cell 30 is "off" so that no current flows between its source and drain. If the threshold voltage of the memory cell 30 is low (e.g. 2 to 3) V, the memory cell 30 is "on" so that a current flows between its source and drain. Read of the information can be made on the basis of the presence or absence (large or small) of the current. But, if the voltage applied to the drain of the memory cell 30 (i.e. bit line 302) is 1 V or more, erroneous write may occur because the drain voltage (i.e. the voltage at the bit line 302) is 5 V. (see Document No. 6)
As compared with the first prior art device shown FIGS. 8 and 9, the second prior art device has an advantage that a transistor for separation is not required in selective writing for a memory cell, but has a defect in that a large current is required for the drain of a memory cell because CHE injection is used in writing. In writing by using the FN tunnel current, a required current is low, so that it is possible to operate the memory by using a single power supply of e.g. 3 V, with a boosting circuit such as a charge pump circuit in an integration circuit. On the other hand, in write from the drain using the CHE injection, lowering of the drain voltage is limited because of the necessity of generating hot electrons. For example, even if the minimum machining size in an integrated circuit is lowered from about 0.8.mu. to 0.5.mu., the required drain voltage can be only reduced from 6 to 7 V to 5 V. Otherwise, even if the drain voltage in writing by using the CHE injection can be reduced to 3 V or so, erroneous read due to the drain voltage is likely to occur in a read operation. This results in less reliability of a memory cell array. In short, in the prior arts, under the restriction of using a single power source for operation (writing and reading), the writing using CHE injection makes it more difficult to reduce the power supply voltage than the writing using the FN tunnel current.
Incidentally, an example of the EEPROM using the FN tunnel effect for writing and erasing is disclosed in U.S. Pat. No. 5,122,985 (Document No.9).